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Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
FEATURES
* 10 single ended LVCMOS/LVTTL outputs, 7 typical output impedance * LVPECL clock input pair * PCLK, nPCLK supports the following input levels: LVPECL, CML, SSTL * Maximum input frequency: 250MHz * Output skew: 120ps (maximum) * Part-to-part skew: 700ps (maximum) * Multiple frequency skew: 320ps (maximum) * 3.3V core, 3.3V or 2.5V output supply modes * -40C to 85C ambient operating temperature
ICS87946I-01
GENERAL DESCRIPTION
The ICS87946I-01 is a low skew, /1, /2 Clock Generator and a member of the HiPerClockSTM HiPerClockSTM family of High Performance Clock Solutions from ICS. The ICS87946I-01 has one LVPECL clock input pair. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50 series or parallel terminated transmission lines. The effective fanout can be increased from 10 to 20 by utilizing the ability of the outputs to drive two series terminated lines.
ICS
The divide select inputs, DIV_SELx, control the output frequency of each bank. The outputs can be utilized in the /1, /2 or a combination of /1 and /2 modes. The master reset input, MR/nOE, resets the internal frequency dividers and also controls the active and high impedance states of all outputs. The ICS87946I-01 is characterized at 3.3V core/3.3V output and 3.3V core/2.5V output. Guaranteed bank, output and partto-part skew characteristics make the ICS87946I-01 ideal for those clock distribution applications demanding well defined performance and repeatability.
BLOCK DIAGRAM
PCLK nPCLK DIV_SELA 0 QB0:QB2 1 DIV_SELB 0 QC0:QC3 1 DIV_SELC MR/nOE /1 /2 0 QA0:QA2 1
PIN ASSIGNMENT
MR/nOE GND GND VDDA VDDA QA0 QA1 QA2
32 31 30 29 28 27 26 25 nc VDD PCLK nPCLK DIV_SELA DIV_SELB DIV_SELC GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDDC QC0 GND QC1 VDDC QC2 GND QC3
24 23 22
GND QB0 VDDB QB1 GND QB2 VDDB VDDC
ICS87946I-01
21 20 19 18 17
32-Lead LQFP 7mm x 7mm x 1.4mm package body Y Package Top View
87946AYI-01
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1
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Type Unused Power Input Input Input Input Input Power Power Pullup Description No connect. Core supply pin. Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. Controls frequency division for Bank A outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank B outputs. Pulldown LVCMOS / LVTTL interface levels. Controls frequency division for Bank C outputs. Pulldown LVCMOS / LVTTL interface levels. Power supply ground. Output supply pins for Bank C outputs.
ICS87946I-01
TABLE 1. PIN DESCRIPTIONS
Number 1 2 3 4 5 6 7 8, 11, 15, 20, 24, 27, 31 9, 13, 17 10, 12, 14, 16 18, 22 Name nc VDD PCLK nPCLK DIV_SELA DIV_SELB DIV_SELC GND VDDC QC0, QC1, QC2, QC3 VDDB QB2, QB1, QB0 VDDA QA2, QA1, QA02,
Bank C outputs. LVCMOS / LVTTL interface levels. Output 7 typical output impedance. Power Output supply pins for Bank B outputs. Bank B outputs. LVCMOS / LVTTL interface levels. 19, 21, 23 Output 7 typical output impedance. Power Output supply pins for Bank A outputs. 25, 29 26, 28, Bank A outputs. LVCMOS / LVTTL interface levels. Output 30 7 typical output impedance. Active HIGH Master Reset. Active LOW Output Enable. When logic HIGH, the internal dividers are reset and the outputs are tri-stated 32 MR/nOE Input Pulldown (HiZ). When logic LOW, the internal dividers and the outputs are enabled. LVCMOS / LVTTL interface levels. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN CPD ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output); NOTE 1 Output Impedance Test Conditions Minimum Typical 4 51 51 VDD, VDDx = 3.465V 5 7 23 12 Maximum Units pF K K pF
NOTE 1: VDDx denotes VDDA, VDDB, VDDC.
TABLE 3. FUNCTION TABLE
MR/nOE 1 0 0 0 0 0 0
87946AYI-01
Inputs DIV_SELA DIV_SELB X X 0 X 1 X X 0 X 1 X X X X
DIV_SELC X X X X X 0 1
QA0:QA2 Hi Z fIN/1 fIN/2 Active Active Active Active
Outputs QB0:QB2 Hi Z Active Active fIN/1 fIN/2 Active Active
QC0:QC3 Hi Z Active Active Active Active fIN/1 fIN/2
REV. A NOVEMBER 21, 2003
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2
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
4.6V -0.5V to VDD + 0.5 V -0.5V to VDD + 0.5V 47.9C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ICS87946I-01
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, VO Package Thermal Impedance, JA Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol VDD VDDx IDD IDDx Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Output Supply Current; NOTE 2 Test Conditions Minimum 3.135 3.135 Typical 3.3 3.3 Maximum 3.465 3.465 54 23 Units V V mA mA
NOTE 1: VDDx denotes VDDA, VDDB, VDDC. NOTE 2: IDDx denotes IDDA, IDDB, IDDC.
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol VIH VIL IIH IIL VOH VOL IOZL Parameter Input High Voltage Input Low Voltage Input DIV_SELA, DIV_SELB, High Current DIV_SELC, MR/nOE Input DIV_SELA, DIV_SELB, Low Current DIV_SELC, MR/nOE Output High Voltage; NOTE 1, 2 Output Low Voltage; NOTE 1, 2 Output Tristate Current Low -5 Test Conditions Minimum 2 -0.3 VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDDx = 3.465V VDDx = 2.625V -5 2.6 1.8 0.5 Typical Maximum VDD + 0.3 0.8 150 Units V V A A V V V A
IOZH Output Tristate Current High 5 A NOTE 1: Outputs terminated with 50 to VDDx/2. See Paremeter Measurement Section, "3.3V Output Load Test Circuit". NOTE 2: VDDx denotes VDDA, VDDB, VDDC.
TABLE 4C. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 3.3V5% OR 2.5V5%, TA = -40C TO 85C
Symbol IIH IIL VPP Parameter Input High Current Input Low Current PCLK nPCLK PCLK nPCLK Test Conditions VDD = VIN = 3.465V VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V VDD = 3.465V, VIN = 0V -5 -150 0.3 1 VDD Minimum Typical Maximum 150 5 Units A A A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
87946AYI-01
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3
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions Minimum 3.135 2.375 Typical 3.3 2.5 Maximum 3.465 2.625 54 22 Units V V mA mA
ICS87946I-01
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = -40C TO 85C
Symbol VDD VDDx IDD IDDx Parameter Core Supply Voltage Output Supply Voltage; NOTE 1 Power Supply Current Output Supply Current; NOTE 2
NOTE 1: VDDx denotes VDDA, VDDB, VDDC. NOTE 2: IDDx denotes IDDA, IDDB, IDDC.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDX = 3.3V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Input Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 6 f = 10MHz f 250MHz Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 20% to 80% 400 40 50 2.3 3.1 Test Conditions Minimum Typical Maximum 250 3.8 30 130 320 700 950 60 3 Units MHz ns ps ps ps ps ps % ns ns
tsk(b) tsk(o) tsk(w) tsk(pp)
t R / tF odc tEN
Output Disable Time; NOTE 6 f = 10MHz 3 tDIS NOTE 1: Measured from the differential input crossing point to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87946AYI-01
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4
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Test Conditions f 250MHz Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 Measured on rising edge at VDDx/2 20% to 80% f = 10MHz 350 43 50 Minimum 2.5 Typical 3.2 Maximum 250 3.8 35 120 325 700 800 57 3 Units MHz ns ps ps ps ps ps % ns ns
ICS87946I-01
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V5%, VDDX = 2.5V5%, TA = -40C TO 85C
Symbol fMAX tPD Parameter Input Frequency Propagation Delay; NOTE 1 Bank Skew; NOTE 2, 7 Output Skew; NOTE 3, 7 Multiple Frequency Skew; NOTE 4, 7 Par t-to-Par t Skew; NOTE 5, 7 Output Rise/Fall Time Output Duty Cycle Output Enable Time; NOTE 6
tsk(b) tsk(o) tsk(w) tsk(pp)
tR / tF odc tEN
Output Disable Time; NOTE 6 f = 10MHz 3 tDIS NOTE 1: Measured from the differential input crossing point to VDDx/2 of the output. NOTE 2: Defined as skew within a bank of outputs at the same supply voltages and with equal load conditions. NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions. Measured at VDDx/2. NOTE 4: Defined as skew across banks of outputs operating at different frequencies with the same supply voltages and equal load conditions. NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDx/2. NOTE 6: These parameters are guaranteed by characterization. Not tested in production. NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
87946AYI-01
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5
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS87946I-01
PARAMETER MEASUREMENT INFORMATION
1.65V5%
2.05V5%
1.25V5%
VDD, V DDx
SCOPE
Qx
VDD V DDx
Qx
SCOPE
LVCMOS
GND
LVCMOS
GND
-1.65V5%
-1.25V5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
V
DDx
nPCLK
Qx
2
V
PCLK
PP
Cross Points
V
CMR
V
DDx
Qy
2 tsk(o)
GND
DIFFERENTIAL INPUT LEVEL
OUTPUT SKEW
QX0:QXx
VDDx 2
QBx:QCx
QX0:QXx
tsk(o)
VDDx 2
QAx
tsk()
BANK SKEW
87946AYI-01
MULTIPLE FREQUENCY SKEW
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6
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
ICS87946I-01
PART 1 nQx
nPCLK
V
Qx PART 2 nQy
DDx
2
PCLK
V
Qy
DDx
2 tsk(pp)
QAx,QBx, QCx
VDD 2 t
PD
PART-TO-PART SKEW
PROPAGATION DELAY
V
80% 20% tR
80%
QAx, QBx, QCx
DDx
2 Pulse Width t
PERIOD
Clock Outputs
20% tF
odc =
t PW t PERIOD
OUTPUT RISE/FALL TIME
OUPUT DUTY CYCLE/PULSE WIDTH/PERIOD
87946AYI-01
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7
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR APPLICATION INFORMATION
ICS87946I-01
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K Single Ended Clock Input
PCLK
V_REF
nPCLK
C1 0.1u
R2 1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
87946AYI-01
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8
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
ICS87946I-01
LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
R1 120 R2 120
nPCLK
HiPerClockS PCLK/nPCLK
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm PCLK Zo = 50 Ohm nPCLK LVPECL R1 84 R2 84 HiPerClockS Input
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V R3 1K R4 1K PCLK
R4 125
nPCLK
HiPerClockS PCL K/n PC LK
R1 1K
R2 1K
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
87946AYI-01
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9
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR RELIABILITY INFORMATION
ICS87946I-01
TABLE 6. JAVS. AIR FLOW TABLE
FOR
32 LEAD LQFP
JA by Velocity (Linear Feet per Minute)
0
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8C/W 47.9C/W
200
55.9C/W 42.1C/W
500
50.1C/W 39.4C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS87946I-01 is: 1204
87946AYI-01
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10
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
32 LEAD LQFP
ICS87946I-01
PACKAGE OUTLINE - Y SUFFIX
FOR
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS BBA SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc 0.45 0 --0.05 1.35 0.30 0.09 MINIMUM NOMINAL 32 --1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 --0.75 7 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication 95, MS-026
87946AYI-01
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11
REV. A NOVEMBER 21, 2003
Integrated Circuit Systems, Inc.
LOW SKEW, /1, /2 LVPECL-TO-LVCMOS/LVTTL CLOCK GENERATOR
Marking ICS87946AYI01 ICS87946AYI01 Package 32 Lead LQFP 32 Lead LQFP on Tape and Reel Count 250 per tray 1000 Temperature -40C to 85C -40C to 85C
ICS87946I-01
TABLE 8. ORDERING INFORMATION
Part/Order Number ICS87946AYI-01 ICS87946AYI-01T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 87946AYI-01
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12
REV. A NOVEMBER 21, 2003

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